Improving Testability of Non-Scan Designs during Behavioral Synthesis
نویسندگان
چکیده
We present a behavioral synthesis method aimed at generating testable datapaths. A non-scan testing strategy is targeted. Given performance and area constraints, the system is aimed at seeking among potential design alternatives the one presenting the least testability problems. The backbone of this methodology is a testability analysis method that works at different abstraction levels of the design description -from strictly behavioral domain to purely structural domain-. Considering a partially mapped behavioral specification, the testability analysis identifies the testability problems of the future structure. These problems are solved along the synthesis process, for example during the register allocation/binding task as presented in this paper.
منابع مشابه
Scan Insertion at the Behavioral Level
Improving testability of complex designs through DFT (Design-For-Testability) has been widely investigated for several years. Designers are taking fully advantage of silicon compilers that allow a design to be synthesized given its behavioral description. However, test logic is still considered only once the logic synthesis is accomplished. This does not take fully advantage of the optimization...
متن کاملDesign for Testability Techniques at the Behavioral and Register-Transfer Levels
Improving testability during the early stages of the design ow can have several beneets, including signiicantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high level design methodologies that consider testability during the early (behavior and architecture) stages of the design ow, and their testability beneet...
متن کاملTestability-driven High-level Synthesis
This paper describes a new approach to integrate testability consideration into high-level synthesis. The approach is based on an iterative technique for high-level synthesis which utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. A testability analysis algorithm is used to analyze the intermediate result...
متن کاملA testability analysis for driving architectural synthesis
In this paper, we present a method for analyzing the testability of a circuit during the design process. Given a circuit specification, whatever the level of description from the behavioral level (initial specification) down to the Register Transfer Level (High Level Synthesis process result), the testability analysis returns values which represent the relative difficulty for computing input se...
متن کاملA synthesis for testability scheme for finite state machines using clock control
A new method is proposed for improving the testability of a finite state machine (FSM) during its synthesis. The method exploits clock control to enhance the controllability and observability of machine states. With clock control it is possible to add new state transitions during testing. Therefore, it is easier to navigate between states in the resulting test machine. Unlike prior work, where ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- J. Electronic Testing
دوره 11 شماره
صفحات -
تاریخ انتشار 1997